Computer system provided with wake-up circuit

The invention discloses a computer system provided with a wake-up circuit. The computer system comprises a reset device, the wake-up circuit and a device to be woken up, wherein the wake-up circuit comprises a first inverse logical circuit, a delay circuit, an AND gate circuit and a second inverse logical circuit; the first inverse logical circuit is used for generating an inverse wake-up signal after receiving a wake-up signal transmitted by the reset device; the delay circuit is used for receiving the inverse wake-up signal and transmitting an inverse delay wake-up signal at a first delay time interval; the AND gate circuit is used for transmitting an AND gate wake-up signal after receiving the wake-up signal and the inverse delay wake-up signal; the second inverse logical circuit is used for transmitting a terminal wake-up signal after receiving and inversing the AND gate wake-up signal; and the device to be woken up is used for receiving the terminal wake-up signal to perform a wake-up action.