Shared bit line cross point memory array

The common bit line cross point memory array structure is provided in accordance with the manufacture and use. The memory structure includes a lower word line is above the word line overlies. Is lower between the word line and the upper word line via a bit line is at the first intersection point is formed between the lower word line and a bit line, a second cross point between said bit lines and said upper word line is formed. One characteristic, such as a material having a resistance which can be changed in response to an input voltage is provided to the above, each of the intersections of the bottom of the bit line.