Buried Metal Silicon-on-Insulator Junctionless Transistor for Low Power CMOS Logic Circuits
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[1] I. Yun,et al. 2-D Quantum Confined Threshold Voltage Shift Model for Asymmetric Short-Channel Junctionless Quadruple-Gate FETs , 2021, IEEE Transactions on Electron Devices.
[2] T. Chiang. Junctionless Multiple-Gate (JLMG) MOSFETs: A Unified Subthreshold Current Model to Assess Noise Margin of Subthreshold Logic Gate , 2021, IEEE Transactions on Electron Devices.
[3] V. Hu,et al. Sensitivity Analysis and Design of Negative-Capacitance Junctionless Transistor for High-Performance Applications , 2021, IEEE Transactions on Electron Devices.
[4] B. Raj,et al. Junctionless Silicon Nanotube Tunnel Field Effect Transistor Based Resistive Temperature Detector , 2021, Silicon.
[5] Yao-Jen Lee,et al. Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters , 2020, IEEE Transactions on Electron Devices.
[6] P. Kondekar,et al. Silicon-On-Nothing Electrostatically Doped Junctionless Tunnel Field Effect Transistor (SON-ED-JLTFET): A Short Channel Effect Resilient Design , 2020, Silicon.
[7] Naveen Kumar,et al. Core-Shell Junctionless Nanotube Tunnel Field Effect Transistor: Design and Sensitivity Analysis for Biosensing Application , 2020, IEEE Sensors Journal.
[8] G. C. Patil,et al. Negative capacitance δ ‐bulk planar junctionless transistor for low power applications , 2019, Micro & Nano Letters.
[9] Ganesh C. Patil,et al. Si3N4: HfO2 dual-k spacer bulk planar junctionless transistor for mixed signal integrated circuits , 2018, IET Circuits Devices Syst..
[10] Sajad A. Loan,et al. Planar Junctionless Silicon-on-Insulator Transistor With Buried Metal Layer , 2018, IEEE Electron Device Letters.
[11] G. C. Patil,et al. Novel δ-doped partially insulated junctionless transistor for mixed signal integrated circuits , 2016 .
[12] Roy P. Paily,et al. A Dual-Material Gate Junctionless Transistor With High- $k$ Spacer for Enhanced Analog Performance , 2014, IEEE Transactions on Electron Devices.
[13] S. Qureshi,et al. Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits , 2012, Microelectron. J..
[14] S. Ganguly,et al. Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- $\kappa$ Spacers , 2011, IEEE Electron Device Letters.
[15] Jean-Pierre Colinge,et al. Performance estimation of junctionless multigate transistors , 2010 .
[16] R. Han,et al. A Computational Study of Dopant-Segregated Schottky Barrier MOSFETs , 2010, IEEE Transactions on Nanotechnology.
[17] B. McCarthy,et al. SOI gated resistor: CMOS without junctions , 2009, 2009 IEEE International SOI Conference.
[18] A. Kottantharayil,et al. Optimization of hetero junction n-channel tunnel FET with high-k spacers , 2009, 2009 2nd International Workshop on Electron Devices and Semiconductor Technology.
[19] A. Bindal,et al. The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology , 2007, IEEE Transactions on Nanotechnology.
[20] 裕幸 飯田,et al. International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .