VLSI Design 2004 Table of Contents

[1]  P. R. Mukund,et al.  Chip package co-design of a heterogeneously integrated 2.45 GHz CMOS VCO using embedded passives in a silicon package , 2004, 17th International Conference on VLSI Design. Proceedings..

[2]  Jeffrey T. Draper,et al.  An area-efficient router for the Data-Intensive Architecture (DIVA) system , 2004, 17th International Conference on VLSI Design. Proceedings..

[3]  Madhav P. Desai,et al.  A novel technique towards eliminating the global clock in VLSI circuits , 2004, 17th International Conference on VLSI Design. Proceedings..

[4]  C. P. Ravikumar,et al.  Fast, layout-aware validation of test-vectors for nanometer-related timing failures , 2004, 17th International Conference on VLSI Design. Proceedings..

[5]  Siva G. Narendra,et al.  The influence of process variations on the Halo MOSFETs and its implications on the analog circuit performance , 2004, 17th International Conference on VLSI Design. Proceedings..

[6]  Srinivas Katkoori,et al.  Intra-bus crosstalk estimation using word-level statistics , 2004, 17th International Conference on VLSI Design. Proceedings..

[7]  Minoru Watanabe,et al.  An optically differential reconfigurable gate array with a partial reconfiguration optical system and its power consumption estimation , 2004, 17th International Conference on VLSI Design. Proceedings..

[8]  Sachin Shrivastava,et al.  An efficient approach to crosstalk noise analysis at multiple operating modes , 2004, 17th International Conference on VLSI Design. Proceedings..

[9]  Nathan Ickes,et al.  Design considerations for next generation wireless power-aware microsensor nodes , 2004, 17th International Conference on VLSI Design. Proceedings..

[10]  Pallab Dasgupta,et al.  Property refinement techniques for enhancing coverage of formal property verification , 2004, 17th International Conference on VLSI Design. Proceedings..

[11]  Anshul Kumar,et al.  Performance analysis of inter cluster communication methods in VLIW architecture , 2004, 17th International Conference on VLSI Design. Proceedings..

[12]  Joseph Rayhawk,et al.  At-speed built-in self-repair analyzer for embedded word-oriented memories , 2004, 17th International Conference on VLSI Design. Proceedings..

[13]  Srinjoy Mitra,et al.  Design of amplifier with rail-to-rail CMR with 1 V power supply , 2004, 17th International Conference on VLSI Design. Proceedings..

[14]  Masahiro Fujita,et al.  High level design validation: current practices and future directions , 2004, 17th International Conference on VLSI Design. Proceedings..

[15]  Anshul Kumar,et al.  Synthesis of application specific multiprocessor architectures for process networks , 2004, 17th International Conference on VLSI Design. Proceedings..

[16]  Anupam Basu,et al.  Katha-mala: a voice output communication aid for the children with Severe Speech and Multiple Disorders (SSMI) , 2004, 17th International Conference on VLSI Design. Proceedings..

[17]  Sarma B. K. Vrudhula,et al.  Energy profiler for hardware/software co-design , 2004, 17th International Conference on VLSI Design. Proceedings..

[18]  Martin Margala,et al.  A current sensor for on-chip, non-intrusive testing of RF systems , 2004, 17th International Conference on VLSI Design. Proceedings..

[19]  N. Ranganathan,et al.  Gate sizing and buffer insertion using economic models for power optimization , 2004, 17th International Conference on VLSI Design. Proceedings..

[20]  Sorin A. Huss,et al.  Rapid prototyping for configurable System-on-a-Chip platforms: a simulation based approach , 2004, 17th International Conference on VLSI Design. Proceedings..

[21]  V. Kamakoti,et al.  A parallel architectural implementation of the New Three-Step Search algorithm for block motion estimation , 2004, 17th International Conference on VLSI Design. Proceedings..

[22]  Sarvesh Bhardwaj,et al.  Efficient algorithms for identifying the minimum leakage states in CMOS combinational logic , 2004, 17th International Conference on VLSI Design. Proceedings..

[23]  Ming Xu,et al.  Shrubbery: a new algorithm for quickly growing high-quality Steiner trees , 2004, 17th International Conference on VLSI Design. Proceedings..

[24]  Dinesh Bhatia,et al.  Estimating pre-placement FPGA interconnection requirements , 2004, 17th International Conference on VLSI Design. Proceedings..

[25]  N. Ranganathan,et al.  A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors , 2004, 17th International Conference on VLSI Design. Proceedings..

[26]  Niraj K. Jha,et al.  Profiling driven computation reuse: an embedded software synthesis technique for energy and performance optimization , 2004, 17th International Conference on VLSI Design. Proceedings..

[27]  Michael S. Hsiao,et al.  Enhancing SAT-based Bounded Model Checking using sequential logic implications , 2004, 17th International Conference on VLSI Design. Proceedings..

[28]  C. Venkatesh,et al.  A quasi static model for a simply supported beam in a circuit simulation framework , 2004, 17th International Conference on VLSI Design. Proceedings..

[29]  André Ivanov,et al.  Open defects detection within 6T SRAM cells using a No Write Recovery Test Mode , 2004, 17th International Conference on VLSI Design. Proceedings..