A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR
暂无分享,去创建一个
Gabor C. Temes | Koichi Hamashita | Kaoru Takasuka | Seiji Takeuchi | Jeongseok Chae | Kyehyung Lee | Mitsuru Aniya
[1] Franco Maloberti,et al. 3.4 A 14mW Multi-bit ∆Σ Modulator with 82dB SNR and 86dB DR for ADSL2+ , 2006 .
[2] P. Hurst,et al. A digital background calibration technique for time-interleaved analog-to-digital converters , 1998, IEEE J. Solid State Circuits.
[3] Pieter Rombouts,et al. An approach to tackle quantization noise folding in double-sampling ΣΔ modulation A/D converters , 2003, IEEE Trans. Circuits Syst. II Express Briefs.
[4] Gabor C. Temes,et al. Noise-Coupled Multi-Cell Delta-Sigma ADCs , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[5] K. Lee,et al. Enhanced split-architecture Δ-Σ ADC , 2006 .
[6] W. Black,et al. Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[7] Gabor C. Temes,et al. A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[8] Un-Ku Moon,et al. "Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC , 2006, IEEE Journal of Solid-State Circuits.
[9] Mohamed Dessouky,et al. Very low-voltage digital-audio /spl Delta//spl Sigma/ modulator with 88-dB dynamic range using local switch bootstrapping , 2001 .
[10] R. T. Baird,et al. Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging , 1995 .
[11] G. Temes,et al. Wideband low-distortion delta-sigma ADC topology , 2001 .
[12] Kyehyung Lee,et al. Noise-coupled ADCs , 2006 .
[13] I. Mehr,et al. A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 1999, IEEE Journal of Solid-State Circuits.
[14] Andreas Kaiser,et al. Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping , 2001, IEEE J. Solid State Circuits.
[15] Thomas Burger,et al. A 0.13/spl mu/m CMOS EDGE/UMTS/WLAN Tri-Mode /spl Delta//spl Sigma/ ADC with -92dB THD , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[16] R. Baird,et al. Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .
[17] Gabor C. Temes,et al. Understanding Delta-Sigma Data Converters , 2004 .
[18] Paul R. Gray,et al. An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS , 1993 .
[19] Gabor C. Temes,et al. Enhanced split-architecture delta-sigma ADC , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.
[20] Un-Ku Moon,et al. A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR , 2005, IEEE Journal of Solid-State Circuits.
[21] Miyamoto Masayuki,et al. A 80/100 MS/s 76.3/70.1-dB SNDR ΔΣ ADC for digital TV receivers , 2006 .
[22] Michael M. Miyamoto,et al. A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique , 2006, IEEE Custom Integrated Circuits Conference 2006.
[23] I. Mehr,et al. A 500 msample/s 6–bit Nyquist rate ADC for disk drive read channel applications , 1998 .
[24] Haruo Kobayashi,et al. Explicit analysis of channel mismatch effects in time-interleaved ADC systems , 2001 .
[25] Kenneth W. Martin,et al. High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..
[26] Paul R. Gray,et al. An 8b 85MS/s Parallel Pipeline A/D Converter in 1μm CMOS (Special Section on the 1992 VLSI Circuits Symposium) , 1993 .
[27] B. Larivee,et al. A split-ADC architecture for deterministic digital background calibration of a 16b 1 MS/s ADC , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[28] I. Galton,et al. An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).
[29] S. Paton,et al. A 12 bit Continuous-Time /spl Sigma//spl Delta/ modulator with 400MHz clock and low jitter sensitivity in 0.13 /spl mu/m CMOS , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
[30] W. Snelgrove,et al. Clock jitter and quantizer metastability in continuous-time delta-sigma modulators , 1999 .
[31] F. Maloberti,et al. A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications , 2007, IEEE Journal of Solid-State Circuits.