Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits

This paper proposes the use of Karhunen-Loeve expansion (KLE) for accurate and efficient modeling of intra-die correlations in the semiconductor manufacturing process. We demonstrate that the KLE provides a significantly more accurate representation, of the underlying stochastic process compared to the traditional approach of dividing the layout into grids and applying principal component analysis (PCA). By comparing the results of leakage analysis using both KLE and the existing approaches, we show that using KLE can provide up to 4-5times reduction in the variability space (number of random variables) while maintaining the same accuracy. We also propose an efficient leakage minimization algorithm that maximizes the leakage yield while satisfying probabilistic constraints on the delay

[1]  David Blaauw,et al.  Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations , 2003, ICCAD 2003.

[2]  Costas J. Spanos,et al.  Modeling within-die spatial correlation effects for process-design co-optimization , 2005, Sixth international symposium on quality electronic design (isqed'05).

[3]  Yu Cao,et al.  Mapping statistical process variations toward circuit performance variability: an analytical modeling approach , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[4]  David Blaauw,et al.  Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[5]  Michael Orshansky,et al.  An efficient algorithm for statistical minimization of total power under timing yield constraints , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[6]  Michel Loève,et al.  Probability Theory I , 1977 .

[7]  Yu Cao,et al.  LOTUS: leakage optimization under timing uncertainty for standard-cell designs , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[8]  Vladimir Zolotov,et al.  Gate sizing using incremental parameterized statistical timing analysis , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[9]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[10]  Sachin S. Sapatnekar,et al.  Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal , 2003, ICCAD 2003.

[11]  T. W. Anderson.  An Introduction to Multivariate Statistical Analysis , 1959 .

[12]  Marcel J. M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[13]  R. Ghanem,et al.  Stochastic Finite Elements: A Spectral Approach , 1990 .

[14]  David Blaauw,et al.  Parametric yield estimation considering leakage variability , 2004, Proceedings. 41st Design Automation Conference, 2004..

[15]  Olivier Coudert,et al.  Gate sizing for constrained delay/power/area optimization , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Zhi-Quan Luo,et al.  Robust gate sizing by geometric programming , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[17]  Sarvesh Bhardwaj,et al.  Leakage minimization of nano-scale circuits in the presence of systematic and random variations , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[18]  T. W. Anderson,et al.  An Introduction to Multivariate Statistical Analysis , 1959 .

[19]  Hai Zhou,et al.  A unified framework for statistical timing analysis with coupling and multiple input switching , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[20]  Sani R. Nassif,et al.  Models of process variations in device and interconnect , 2000 .

[21]  Anantha Chandrakasan,et al.  Models of Process Variations in Device and Interconnect , 2001 .