Embedding the Digital Watermarks into FPGA-Projects Containing the Adaptive Logic Modules

The given paper deals with the problem of embedding the digital watermarks into program code of the FPGA chips. A digital watermark gives the possibility to place the extra information hidden from an outside surveillance in the program code FPGA. This can provide the integrity monitoring and monitoring of usage of FPGA program code processes. The matter is that the existing methods of the digital watermark embedding are focused on FPGA, in which basic logic elements contain only a programmable calculating unit LUT and programmable flip-flop. The adaptation of method of the digital watermark embedding to FPGA chips, which have dedicated hard full adders in the composition of basic logic elements, is offered. The analysis of the proposed method implementation has been carried out. It turns out that the usage of the offered method increases the embedded digital watermark size.

[1]  Oleksandr Drozd,et al.  The detection method of probable areas of hardware Trojans location in FPGA-based components of safety-critical systems , 2018, 2018 IEEE 9th International Conference on Dependable Systems, Services and Technologies (DESSERT).

[2]  P. P. Deepthi,et al.  An Integrity Verification System for Images Using Hashing and Watermarking , 2012, 2012 International Conference on Communication Systems and Network Technologies.

[3]  Frank Y. Shih,et al.  Digital Watermarking and Steganography: Fundamentals and Techniques , 2007 .

[4]  Swarup Bhunia,et al.  Reconfigurable computing using content addressable memory for improved performance and resource usage , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[5]  Sergey Feofentovich Tyurin.  LUT’s Sliding Backup , 2019, IEEE Transactions on Device and Materials Reliability.

[6]  David Kleidermacher,et al.  Embedded Systems Security: Practical Methods for Safe and Secure Software and Systems Development , 2012 .

[7]  Oksana Pomorova,et al.  Metamorphic Viruses Detection Technique Based on the the Modified Emulators , 2016, ICTERI.

[8]  Hideharu Amano,et al.  Principles and Structures of FPGAs , 2018, Springer Singapore.

[10]  Swarup Bhunia,et al.  Hardware IP Security and Trust , 2017 .

[11]  Volodymyr Kochan,et al.  Improving of the security of intrusion detection system , 2016, 2016 International Conference on Development and Application Systems (DAS).

[12]  Jessica Fridrich.  Steganography in Digital Media: Preface , 2009 .

[13]  David M. Lewis,et al.  Architectural enhancements in Stratix V™ , 2013, FPGA '13.

[14]  Kostiantyn Zashcholkin,et al.  The Control Technology of Integrity and Legitimacy of LUT-Oriented Information Object Usage by Self-Recovering Digital Watermark , 2015, ICTERI.

[15]  Debdeep Mukhopadhyay,et al.  Hardware Security - Design, Threats, and Safeguards , 2014 .

[16]  A. Drozd,et al.  Checkable FPGA Design: Energy Consumption, Throughput and Trustworthiness , 2019 .

[17]  Oleksandr Martynyuk,et al.  Improving of a Circuit Checkability and Trustworthiness of Data Processing Results in LUT-based FPGA Components of Safety-Related Systems , 2017, ICTERI.

[18]  Dieter Gollmann,et al.  Computer Security , 1979, Lecture Notes in Computer Science.

[19]  William Stallings,et al.  Cryptography and Network Security: Principles and Practice , 1998 .

[20]  Eduardo de la Torre Arnanz,et al.  FPGAs: Fundamentals, Advanced Features, and Applications in Industrial Electronics , 2017 .

[21]  V. Kharchenko,et al.  Security assessment of FPGA-based safety-critical systems: US NRC requirements context , 2015, 2015 International Conference on Information and Digital Technologies.

[22]  Ingemar J. Cox,et al.  Digital Watermarking and Steganography , 2014 .

[23]  Svitlana Hrushko.  Implementing combined finite state machine with heterogeneous field programmable gate array , 2018, 2018 14th International Conference on Advanced Trends in Radioelecrtronics, Telecommunications and Computer Engineering (TCSET).

[24]  Kostiantyn Zashcholkin,et al.  LUT-object integrity monitoring methods based on low impact embedding of digital watermark , 2018, 2018 14th International Conference on Advanced Trends in Radioelecrtronics, Telecommunications and Computer Engineering (TCSET).

[25]  Bo Yan,et al.  On Hard Adders and Carry Chains in FPGAs , 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

[26]  Alexander Barkalov,et al.  Synthesis and Optimization of FPGA-Based Systems , 2014 .

[27]  Matt Bishop,et al.  What Is Computer Security? , 2003, IEEE Secur. Priv..

[28]  Alexander V. Drozd,et al.  Use of Natural LUT Redundancy to Improve Trustworthiness of FPGA Design , 2016, ICTERI.

[29]  B.K. Yi,et al.  Digital signatures , 2006, IEEE Potentials.

[30]  Tsuyoshi Murata,et al.  {m , 1934, ACML.