论文信息 - BICMOS circuit technology for high speed DRAMs

BICMOS circuit technology for high speed DRAMs

In the development of high density DRAMs such as 1 M bit or beyond, it will be increasingly important to achieve high speed, competitive to SRAMs, in addition to low cost per bit. Recently, BIPOLAR CMOS (BICMOS) technology has been proposed for achieving high speed and low power operation, especially SRAMs (1,2).

S. Watanabe | K. Hieda | S. Aritome | K. Sakui | T. Fuse

[1] S. Fujii,et al. A new sense amplifier technique for VLSI dynamic RAM's , 1981, 1981 International Electron Devices Meeting.

[2] G. Sai-Halasz. Alpha-particle-induced soft error rate modeling , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3] Takayuki Kawahara,et al. Comparison of CMOS and BiCMOS 1-Mbit DRAM performance , 1989 .

[4] Kiyoo Itoh,et al. Bipolar CMOS-merged technology for a high-speed 1-Mbit DRAM , 1989 .

[5] I. Masuda,et al. Perspective on BiCMOS VLSIs , 1988 .

[6] R. Hori,et al. A 5 V-only 64K dynamic RAM based on high S/N design , 1980, IEEE Journal of Solid-State Circuits.

[7] Lewis M. Terman,et al. A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate , 1988 .

[8] Kiyoo Itoh,et al. An experimental 1-Mbit BiCMOS DRAM , 1987 .

[9] Yasunao Katayama,et al. A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing , 1989 .

[10] Takayuki Kawahara,et al. Substrate current reduction techniques for BiCMOS DRAM , 1989 .