Hardware prototyping of root raised cosine FIR filter for 2x2 MIMO channel sounder

A root raised cosine (RRC) finite impulse response (FIR) digital filter using Xilinx system generator blockset in simulink environment is presented in this paper. The RRC filter is designed and implemented as a part of BPSK transmitter for CDM based 2x2 MIMO channel sounder. The role of the filter in the transmitter is pulse shaping. Pulse shaping is needed to specify the bandwidth of band limited base band communication system. In this paper, a 32 order square root FIR digital filter is designed and implemented in Xilinx FPGA.

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