A high speed analog 50 /spl Omega/ line driver in digital CMOS technology

A single-ended analog buffer designed to drive 50 /spl Omega/ loads is described. The circuit consists of a common source output pair driven by a pair of differential error amplifiers which significantly reduce the output impedance. This technique improves the drive capability of operational amplifiers. This paper demonstrates the feasibility of using the circuit technique as a stand alone buffer. The amplifier has been fabricated in a 2 /spl mu/m digital CMOS technology and occupies an area of 190 mil/sup 2/. The amplifier has a /spl sim/50 /spl Omega/ output impedance and an upper half power frequency of 23 MHz when driving a 50 /spl Omega//50 pF load and consumes 102 mW from /spl plusmn/5 V supplies.

[1]  Robert G. Meyer,et al.  Analysis and Design of Analog Integrated Circuits , 1993 .

[2]  R. Koch,et al.  A Class AB High Swing CMOS Power Amplifier , 1991, ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference.

[3]  K. E. Brehmer,et al.  Large swing CMOS power amplifier , 1983 .

[4]  Randall L. Geiger,et al.  VLSI Design Techniques for Analog and Digital Circuits , 1989 .

[5]  Deog-Kyoon Jeong,et al.  Class-AB large-swing CMOS buffer amplifier with controlled bias current , 1993 .

[6]  J.A. Fisher.  A high-performance CMOS power amplifier , 1985, IEEE Journal of Solid-State Circuits.