Novel static differential ultra low-voltage and high speed domino CMOS logic

In this paper we present a novel static differential ultra low-voltage (ULV) CMOS logic style. Simulated data for the logic style is presented and compared to related ULV logic styles and complementary CMOS gates. The proposed logic style is aimed for high speed serial adders in ultra low-voltage applications. In terms of energy delay product (EDP) the logic style offers a significant improvement compared to complementary CMOS. The proposed differential ULV logic style offers improved noise margin compared to simpler ULV logic styles. The simulated data presented is obtained using Hspice simulator and applying a 90nm TSMC CMOS process.

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