论文信息 - Applying Folding & Register Minimization Transformation on DFG and Generating Verilog HDL Code - 字舞流文

Applying Folding & Register Minimization Transformation on DFG and Generating Verilog HDL Code

Shoab A. Khan | Farhan Shafiq | Faisal Moeen | S. Khan | F. Shafiq | Faisal Moeen

[1] Yong-Bin Kim,et al. A Sub-1V Power Supply Sub-bandgap with an Extended Voltage and Temperature Range , 2005 .