Design and Synthesis of High Performance Vedic DSP Processor

To satisfy the prerequisite of rapid speed signal processing design of high performance DSP processor is renowned. This paper represents a novel design and FPGA based pursuit of 64 bit DSP processor. The proposed design implicates multistage pipeline architecture and vedic algorithms to improve the speed. The DSP processor is rich with multiple application specific instructions (ASIP). The verilog HDL is used and the validated through extensive simulation. Synthesis results and attainment scrutiny of each systems components confirmed significant performance meliorism in the proffered DSP processor over the extant one.. General Terms Urdhava Tiryagbhyam multiplier Nikhilam sutra and paravarty sutra kogge stone adder et. al.

[1]  M. Nagaraju,et al.  High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics , 2013 .

[2]  Sandeep Saini,et al.  Binary division algorithm and high speed deconvolution algorithm (Based on Ancient Indian Vedic Mathematics) , 2014, 2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON).

[3]  Deepak Nagaria,et al.  Design of High Performance FIR FilterUsing Vedic Mathematics in MATLAB , 2014 .

[4]  A. Dandapat,et al.  High speed ASIC design of complex multiplier using Vedic Mathematics , 2011, IEEE Technology Students' Symposium.

[5]  Ashutosh Gupta,et al.  Energy efficient and high performance 64-bit Arithmetic Logic Unit using 28nm technology , 2015, 2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

[6]  Zhiying Wang,et al.  Design of a Configurable Embedded Processor Architecture for DSP Functions , 2005, 11th International Conference on Parallel and Distributed Systems (ICPADS'05).

[7]  E. O'Malley,et al.  A 16-bit fixed-point digital signal processor for digital power converter control , 2005, Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, 2005. APEC 2005..

[8]  Ankita Sharma,et al.  16-Order IIR Filter Design using Vedic Mathematic Technique , 2014 .

[9]  Vaijyanath Kunchigi,et al.  32-BIT MAC UNIT DESIGN USING VEDIC MULTIPLIER , 2013 .

[10]  Johann Großschädl,et al.  A single-cycle (32/spl times/32+32+64)-bit multiply/accumulate unit for digital signal processing and public-key cryptography , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

[11]  Abhyarthana Bisoyi,et al.  Comparison of a 32-bit Vedic multiplier with a conventional binary multiplier , 2014, 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies.

[12]  Chan Mo Kim,et al.  Multiplier design based on ancient Indian Vedic Mathematics , 2008, 2008 International SoC Design Conference.

[13]  Tushar Shukla,et al.  High speed multiplier for FIR filter design using window , 2014, 2014 International Conference on Signal Processing and Integrated Networks (SPIN).

[15]  N K.,et al.  Design A DSP Operations Using Vedic Mathematics , 2014 .

[16]  Rajesh Mahle,et al.  Design a DSP operations using vedic mathematics , 2013, 2013 International Conference on Communication and Signal Processing.

[17]  Jusung Park,et al.  Design and implementation of 16-bit fixed point digital signal processor , 2008, 2008 International SoC Design Conference.

[18]  Siba Kumar Panda,et al.  A Novel Vedic Divider Architecture with Reduced Delay for VLSI Applications , 2015 .