论文信息 - A high speed 0.25 /spl mu/m 64-bit CMOS adder design

A high speed 0.25 /spl mu/m 64-bit CMOS adder design

A fast 64-bit dynamic adder has been designed for high performance microprocessors in 2.5-V 0.25-/spl mu/m 1-poly 5-metal CMOS technology. Fast carry signals can only be obtained by fast G (Generation) and P (Propagation) terms. Integrating dynamic CMOS logic, the Kogge & Stone algorithm and a new circuit architecture, the adder comprises 7 k FETs and has 660 ps addition latency under nominal conditions.

Mao Zhi-gang | Ye Yi-zheng | Lai Feng-chang | Sun Xu-guang

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