Multi-way FSM decomposition based on interconnect complexity

Various strategies for multi-way general decomposition have been investigated in the past. These strategies differ in how they reflect the cost of a logic-level implementation. The authors are concerned with the lower bound on the number of interconnecting wires which must exist when a machine is decomposed into several submachines. From a VLSI implementation point of view having a cost function based at least in part on interconnect complexity would be advantageous. The authors present a way to establish this bound for the multi-way decomposition of an arbitrary machine and tabulate the bound for a number of benchmarks. This tabulation shows that many large benchmarks are indeed highly decomposable from an interconnect point of view.<<ETX>>