A Measurement and Simulation Based Methodology for Cache Performance Modeling and Tuning
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[1] 장훈,et al. [서평]「Computer Organization and Design, The Hardware/Software Interface」 , 1997 .
[2] Margaret Martonosi,et al. Integrating performance monitoring and communication in parallel computers , 1996, SIGMETRICS '96.
[3] Dionisios N. Pnevmatikatos,et al. Cache performance of the SPEC92 benchmark suite , 1993, IEEE Micro.
[4] D.A. Reed,et al. An Integrated Compilation and Performance Analysis Environment for Data Parallel Programs , 1995, Proceedings of the IEEE/ACM SC95 Conference.
[5] Todd C. Mowry,et al. Tolerating latency in multiprocessors through compiler-inserted prefetching , 1998, TOCS.
[6] John L. Hennessy,et al. MTOOL: a method for detecting memory bottlenecks , 1991, SIGMETRICS '91.
[7] Mary K. Vernon,et al. LoPC: modeling contention in parallel algorithms , 1997, PPOPP '97.
[8] S. Turner,et al. Performance Analysis Using the MIPS R10000 Performance Counters , 1996, Proceedings of the 1996 ACM/IEEE Conference on Supercomputing.
[9] Yong Luo,et al. Development and Validation of a Hierarchical Memory Model Incorporating CPU- and Memory-Operation Overlap , 1997 .
[10] Mary K. Vernon,et al. Poems: end-to-end performance design of large parallel adaptive computational systems , 1998, WOSP '98.
[11] Pradip Bose,et al. Performance Analysis and Its Impact on Design , 1998, Computer.
[12] Cos S. Ierotheou,et al. Computer Aided Parallelisation Tools (CAPTools) - Conceptual Overview and Performance on the Parallelisation of Structured Mesh Codes , 1996, Parallel Comput..
[13] PattersonDavid,et al. LogP: towards a realistic model of parallel computation , 1993 .
[14] Sharad Malik,et al. Cache miss equations: an analytical representation of cache misses , 1997, ICS '97.
[15] Margaret Martonosi,et al. Tuning Memory Performance of Sequential and Parallel Programs , 1995, Computer.
[16] Pamela P. Walatka. WebToons: a method for organizing and humanizing Web documents , 1996, SIGGRAPH '96.
[17] Mahmut T. Kandemir,et al. Changing Interaction of Compiler and Architecture , 1997, Computer.
[18] Yong Luo,et al. Development and validation of a hierarchical memory model incorporating CPU- and memory-operation overlap model , 1998, WOSP '98.
[19] Adolfy Hoisie,et al. Performance and Scalability Analysis of Teraflop-Scale Parallel Architectures Using Multidimensional Wavefront Applications , 2000, Int. J. High Perform. Comput. Appl..
[20] John L. Hennessy,et al. The accuracy of trace-driven simulations of multiprocessors , 1993, SIGMETRICS '93.