A suitable FPGA implementation of floating-point matrix inversion based on Gauss-Jordan elimination

This work presents an architecture to compute matrix inversions in a hardware reconfigurable FPGA with single-precision floating-point representation, whose main unit is the processing component for Gauss-Jordan elimination. This component consists of other smaller arithmetic units, organized to maintain the accuracy of the results without the need to internally normalize and de-normalize the floating-point data. The implementation of the operations and the whole unit take advantage of the resources available in the Virtex-5 FPGA. The performance and resource consumption of the implementation are improvements in comparison with different more elaborated architectures whose implementations are more complex for low cost applications. Benchmarks are done with solutions implemented previously in FPGA and software, such as Matlab.

[1]  Joseph R. Cavallaro,et al.  FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..

[2]  Ryan Kastner,et al.  An FPGA Design Space Exploration Tool for Matrix Inversion Architectures , 2008, 2008 Symposium on Application Specific Processors.

[3]  Zoran A. Salcic,et al.  A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study , 2006, EURASIP J. Adv. Signal Process..

[4]  A. Happonen,et al.  GSM channel estimator using a fixed-point matrix inversion algorithm , 2005, International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005..

[5]  M. Ylinen,et al.  A fixed-point implementation of matrix inversion using Cholesky decomposition , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[6]  Viktor Öwall,et al.  A scalable pipelined complex valued matrix inversion architecture , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[7]  Mário P. Véstias,et al.  Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[8]  Poras T. Balsara,et al.  VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[9]  K. Dharmarajan,et al.  Parallel VLSI algorithm for stable inversion of dense matrices , 1989 .

[10]  Johan Eilert,et al.  Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[11]  R. Gregory Taylor,et al.  Modern computer algebra , 2002, SIGA.

[12]  Horácio C. Neto,et al.  On Reconfigurable Architectures for Efficient Matrix Inversion , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[13]  Carlos H. Llanos,et al.  Parameterizable floating-point library for arithmetic operations in FPGAs , 2009, SBCCI.

[14]  Diego Felipe,et al.  Implementação em VHDL de uma biblioteca parametrizável de operadores aritméticos em ponto flutuante para ser usada em problemas de robótica , 2009 .