A Review on Cellular Automata Based Bit Error Correcting Codes

In recent years, large volumes of data are transferred between a computer system and various subsystems through digital logic circuits and interconnected wires. And there always exist potential errors when data are transferred due to electrical noise, device malfunction, or even timing errors. In general, parity checking circuits are usually employed for detection of single-bit errors. However, it is not sufficient to enhance system reliability and availability for efficient error detection and necessary to detect and further correct errors up to a certain level within the affordable cost. To handle a large number of information bits, the associated circuits become quite complex and irregular on the other the CA’s circuit structure having simple, regular and modular propertiesis amenable for VLSI implementation.The purpose of this paper is investigateen coding and decodingof bit error correction methods using the properties of CA. The results show that these schemesarepossible to correct errors by the easy and fast analysis of syndrome.