Alpha-Induced Multiple Cell Upsets in Standard and Radiation Hardened SRAMs Manufactured in a 65 nm CMOS Technology

Accelerated alpha-soft error rate (SER) measurements are carried out on regular and radiation-hardened SRAMs in a 65 nm CMOS technology. Results are first compared to previous experimental radiation data in 130 nm and 90 nm. Second, the SER increase measured in 65 nm is investigated through (i) multiple cell upsets (MCU) counting and classification from experimental bitmap errors and (ii) full 3-D device simulations on SRAM bitcells to assess the PMOS-off sensitivity and the NMOS SEU threshold LET (LETth) of each tested technologies. Finally, process changes are also scanned to shed light on the 65 nm SRAM response to alpha particles

[1]  R. Baumann The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction , 2002, Digest. International Electron Devices Meeting,.

[2]  E. Cannon,et al.  SRAM SER in 90, 130 and 180 nm bulk and SOI technologies , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[3]  K. Soumyanath,et al.  Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/ , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[4]  J. Maiz,et al.  Alpha-SER modeling and simulation for sub-0.25 /spl mu/m CMOS technology , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[5]  N. Seifert,et al.  Chip-level soft error estimation method , 2005, IEEE Transactions on Device and Materials Reliability.

[6]  J. C. Pickel,et al.  Rate prediction for single event effects-a critique , 1992 .

[7]  K. Bernstein,et al.  Soft error rate scaling for emerging SOI technology options , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[8]  K. Kumagai,et al.  Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[9]  J. Moll,et al.  Breakdown mechanism in short-channel MOS transistors , 1978, 1978 International Electron Devices Meeting.

[10]  Robert Ecoffet,et al.  Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations , 1999 .

[11]  Changhong Dai,et al.  Impact of CMOS process scaling and SOI on the soft error rates of logic processes , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

[12]  R. Harboe-Sorensen,et al.  Multiple-Bit Upset Analysis in 90 nm SRAMs: Heavy Ions Testing and 3D Simulations , 2007, IEEE Transactions on Nuclear Science.

[13]  P. Roche,et al.  Alpha induced SEU and MBU rates evaluation for advanced SRAMs by Monte-Carlo simulations , 2005, 2005 8th European Conference on Radiation and Its Effects on Components and Systems.

[14]  J. Tschanz,et al.  Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation , 2003, IEEE International Electron Devices Meeting 2003.

[15]  Guillaume Hubert,et al.  Detailed analysis of secondary ions' effect for the calculation of neutron-induced SER in SRAMs , 2001 .

[16]  P. Dodd,et al.  Various SEU conditions in SRAM studied by 3-D device simulation , 2001 .

[17]  T. Noguchi,et al.  Comprehensive study on layout dependence of soft errors in CMOS latch circuits and its scaling trend for 65 nm technology node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[18]  F. W. Sexton,et al.  Contribution of device simulation to SER understandfng , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[19]  F. Wrobel,et al.  Monte-Carlo simulations to quantify neutron-induced multiple bit upsets in advanced SRAMs , 2005, IEEE Transactions on Nuclear Science.

[20]  Robert Ecoffet,et al.  SEU response of an entire SRAM cell simulated as one contiguous three dimensional device domain , 1998 .

[21]  F. Jacquet,et al.  An alpha immune and ultra low neutron SER high density SRAM , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[22]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[23]  G. Gasiot,et al.  Impacts of front-end and middle-end process modifications on terrestrial soft error rate , 2005, IEEE Transactions on Device and Materials Reliability.