Design and Implementation of a 40-ns 16-kb EEPROM

A 2 k×8 bits EEPROM based on 0.35 μm CMOS process is developed, which operates from a single 3.3 V power supply. Several design techniques are summarized. An improved readout circuit consisting of sensing amplifier (SA), bit-line decoding and word-line charge/discharge circuit to minimize the access time is described in particular, along with the approach to optimizing the programming operation. Emphasis is made on the on-chip high-voltage generation circuit, and a zero threshold voltage charge pump is proposed, which can improve the performance without additional design and process complexity. A 40 ns typical access time and 2 ms page programming time are achieved. The cell size is 11.27 μm~2 and chip size is about 1.5 mm~2.