A novel 40-Gb/S PAM4 transmitter with power-efficient pre-emphasis

This paper presents a 65-nm CMOS 40-Gb/s PAM4 transmitter with power-efficient pre-emphasis. Switchable current sources are used in the pre-emphasis tap to eliminate power wasting. The pre-emphasis tap only injects current to the output nodes upon the voltage level transition of the output signal. Current does not flow through the pre-emphasis tap when there is no transition. Simulation results show that with insertion loss of the channel being 20.2 dB at 20 GHz, an eye height of 120 mV and an eye width of 30 ps are achieved. The driver consumes only 18.3 mW, which is equivalent to 0.46-pJ/b.

[1]  D.A. Johns,et al.  A CMOS 10-gb/s power-efficient 4-PAM transmitter , 2004, IEEE Journal of Solid-State Circuits.

[2]  Jri Lee,et al.  Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data , 2008, IEEE Journal of Solid-State Circuits.

[3]  Ieee Staff,et al.  2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) , 2015 .

[4]  J. Silva-Martinez,et al.  Low-voltage low-power LVDS drivers , 2005, IEEE Journal of Solid-State Circuits.