论文信息 - IMPROVING MEMORY HIERARCHY PERFORMANCE IN SYNCHRONOUS DESIGN

IMPROVING MEMORY HIERARCHY PERFORMANCE IN SYNCHRONOUS DESIGN

This paper surveys techniques used to improve memory hierarchy performance in the synchronous design. A number of commercial cache implementations are also described and discussed. The paper concludes by discussing candidate techniques that need to be studied in more detail for use in an asynchronous environment.

Rakesh Kumar | Bhaskar Nautiyal | Saurabh Rawat | Anushree Sah | Sumit Pundir

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