Energy estimation of nested loop programs

An energy estimation methodology when mapping nested loop programs onto fine grained VLSI architectures is proposed. Regular loop algorithms with uniform data dependencies have some power consumption-friendly properties. E.g., using linear allocation and scheduling functions (loop transformations) results in distributed computations and communication between nearest neighbor processors. So, data can be stored locally in each processor which is essential for low power VLSI designs. We show that the chosen mapping has a significant influence on the consumed energy. Our estimation approach identifies statements with decreased operand switching activity. For these statements with reduced activity, a lower power consumption value can be directly obtained from a generated table based model to refine the estimation. Experimental results fortify the significant influence of the mapping (loop transformation).