A data driven high performance Time to Digital Converter

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (25ps 800ps bin) has been implemented in a 0.25um CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 98ps. Finally, finer time interpolation is obtained using an on-chip R-C delay line. Time measurements are processed and buffered in a data driven architecture based on time tags. This results in a highly flexible triggered or non-triggered TDC, which can be used in many different applications.