Temperature behavior of combination selection based mismatch calibration with 65 nm CMOS technology

The temperature behaviour of a combination selection based mismatch calibration is discussed. The functionality of the calibration structure has already been presented. Clear benefits in implementation area and accuracy can be reached when using mismatch calibration based on combination selection of fine-tuning transistors. However, with the high accuracy requirements, the effects of temperature must be taken into the account. Temperature compensation circuitry for combination selection based mismatch calibration is developed, designed and simulated in digital 65 nm CMOS technology. The new temperature compensated and mismatch calibrated current source achieves 99% accuracy in 4σ confidence over the temperature range of 40 degrees in centigrade. This range can still be extended by recalibrating the current source in intervals of 20 degrees in centigrade.

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