Thermal optimization in multi-granularity multi-core floorplanning

Multi-core microarchitectures require a careful balance between many competing objectives to achieve the highest possible performance. Integrated Early Analysis is the consideration of all of these factors at an early stage. Toward this goal, this work presents the first adaptive multi-granularity multi-core microarchitecture-level floorplanner that simultaneously optimizes temperature and performance, and considers memory bus length. We include simultaneous optimization at both the module-level and the core/cache-bank level. Related experiments show that our methodology is effective for optimizing multi-core architectures.

[1]  Jason Cong,et al.  Microarchitecture evaluation with physical planning , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[2]  Seda Ogrenci Memik,et al.  Physical aware frequency selection for dynamic thermal management in multi-core systems , 2006, ICCAD.

[3]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, ICCAD 2004.

[4]  Yoji Kajitani,et al.  VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[6]  C. Nicopoulos,et al.  Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, ISCA 2006.

[7]  James D. Meindl,et al.  A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001 , 1996, Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit.

[8]  Radu Marculescu,et al.  Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach , 2005, Design, Automation and Test in Europe.

[9]  Lei He,et al.  Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects , 2004, Proceedings. 41st Design Automation Conference, 2004..

[10]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[11]  Sung Kyu Lim,et al.  Bus-aware microarchitectural floorplanning , 2008, 2008 Asia and South Pacific Design Automation Conference.

[12]  John A. Darringer Multi-Core Design Automation Challenges , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[13]  Kevin Skadron,et al.  HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Hsien-Hsin S. Lee,et al.  Profile-guided microarchitectural floor planning for deep submicron processor design , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  José González,et al.  Understanding the Thermal Implications of Multi-Core Architectures , 2007, IEEE Transactions on Parallel and Distributed Systems.

[16]  Luca Benini,et al.  Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[17]  Ying Chen,et al.  Microarchitecture-aware floorplanning using a statistical design of experiments approach , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[18]  J. Meigs,et al.  WHO Technical Report , 1954, The Yale Journal of Biology and Medicine.

[19]  Mely Chen Chi,et al.  An effective soft module floorplanning algorithm based on sequence pair , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[20]  Sung Kyu Lim,et al.  Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.