Compact hardware architectures for BLAKE and LAKE hash functions

BLAKE, one of SHA-3 candidates, and LAKE hash functions show the characteristic that the block length of the internal state is double its initial and final states, which means more registers are required for the implementation of the hash functions. In this paper, we explore shift register based compact hardware architectures for the two hash functions. This includes the 32−, 64−, and 128-bit datapath architectures for BLAKE. We provide post Place&Route performance results on both ASIC and FPGA platforms. The power consumption for each design is also given. Our results show that BLAKE has comparable performance when compared with the previous standard hash function of Whirlpool and less performance advantages over SHA-256. The results also indicate that BLAKE outperforms LAKE in the hardware implementation.