SRAM Cell Stability: A Dynamic Perspective

SRAM cell stability assessment is traditionally based on static criteria of data stability requiring three coincident points in DC butterfly curves. This definition is based on static (DC) characteristics of the cell transistors. We introduce the dynamic criteria of cell data stability knowing that the cell operates in a dynamic environment alternating between access and non-access conditions. The proposed definition of the dynamic data stability criteria introduces a new bound for the cell static noise margin (SNM). It reveals that the true noise margin of the cell can be made considerably higher than the conventional SNM once the cell access time is sufficiently shorter than the cell time-constant. This phenomena can be used to extend the noise margin in (partial) subthreshold SRAMs. Moreover, a simulation method for verification of the dynamic data stability criteria is presented. Silicon measurement results in 130 nm CMOS technology confirms the concept of dynamic data stability and designer's ability to trade timing and static parameters . Finally, it is shown that the long time constant due to the subthreshold operation of the cell can be exploited to maintain data stability with proper choice of access and recovery time.

[1]  Hendrikus J. M. Veendrick,et al.  The behaviour of flip-flops used as synchronizers and prediction of their failure rate , 1980 .

[2]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[3]  M. Sharifkhani,et al.  An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 $\mu$m CMOS , 2009, IEEE Journal of Solid-State Circuits.

[4]  Masahiro Nomura,et al.  A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications , 2006, IEEE Journal of Solid-State Circuits.

[5]  J. Lohstroh.  Static and dynamic noise margins of logic circuits , 1979 .

[6]  H. Pilo,et al.  An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage , 2007, IEEE Journal of Solid-State Circuits.

[7]  Mohammad Sharifkhani,et al.  Dynamic Data Stability in Low-power SRAM Design , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[8]  K. Takeda,et al.  A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[9]  Wim Dehaene,et al.  A Low Power Embedded SRAM for Wireless Applications , 2006 .

[10]  M. Khellah,et al.  Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[11]  Mohammad Sharifkhani,et al.  Segmented Virtual Ground Architecture for Low-Power Embedded SRAM , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  V. A. Pliss.  Nonlocal Problems of the Theory of Oscillations , 1966 .

[13]  Mohammad Sharifkhani,et al.  Dynamic data stability in SRAM cells and its implications on data stability tests , 2006, 2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06).

[14]  T. Wada,et al.  An analytical access time model for on-chip cache memories , 1992 .

[15]  Kiyoo Itoh,et al.  Vlsi Memory Chip Design , 2006 .

[16]  Noriyuki Suzuki,et al.  A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture , 1992 .

[17]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[18]  J. Lohstroh,et al.  Worst-case static noise margin criteria for logic circuits and their mathematical equivalence , 1983, IEEE Journal of Solid-State Circuits.

[19]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .