Impact of slurry in Cu CMP (chemical mechanical polishing) on Cu topography of Through Silicon Vias (TSVs), re-distribution layers, and Cu exposure
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P. Tzeng | M. Kao | J. Lau | J. Chen | S. C. Chen | C. Y. Wu | C. C. Chen | Y. Hsin | Y. Hsu | S. Shen | S. Liao | C. Ho | C. H. Lin | T. Ku
[1] Y. Yamaji,et al. Process integration of 3D chip stack with vertical interconnection , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).
[2] Kazumasa Tanida,et al. Development of less expensive process technologies for three-dimensional chip stacking with through-vias , 2004 .
[3] V. Kripesh,et al. Cu via Exposure by Backgrinding for TSV Applications , 2007, 2007 9th Electronics Packaging Technology Conference.
[4] R. Beica,et al. Through silicon via copper electrodeposition for 3D integration , 2008, Electronic Components and Technology Conference.
[5] Vempati Srinivasa Rao,et al. TSV interposer fabrication for 3D IC packaging , 2009, 2009 11th Electronics Packaging Technology Conference.
[6] D. Malta,et al. Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).