Redundant binary Booth recoding

We investigate the efficiencies attainable pursuing Booth recoding directly from redundant binary input with limited carry propagation. As a digit conversion problem we extend the important result that each radix 4 Booth recoded digit can be determined from 5 consecutive input signed bits to obtain that each radix 2/sup k/ Booth recoded digit can be determined from 2k+1 consecutive input signed bits and prove this to be the minimum possible for any k/spl ges/2. Analysis of alternative bit pair encodings of signed bits yields the improved result that each radix 2/sup k/ Booth recoded digit can be determined from only 2k encoded bit pairs employing sign and magnitude bit encoding, a result which does not extend to conventional borrow-save or carry-save redundant binary digit encodings. Radices 4 and 8 gate level designs are illustrated for alternative encodings, with our signed bit design shown to yield smaller depth and fewer gates than existing redundant binary Booth recoding circuits from the literature.<<ETX>>

[1]  Naofumi Takagi Arithmetic unit based on a high-speed multiplier with a redundant-binary addition tree , 1991, Optics & Photonics.

[2]  Debjit Das Sarma,et al.  Faithful bipartite ROM reciprocal tables , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[3]  Homayoon Sam,et al.  A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations , 1990, IEEE Trans. Computers.

[4]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[5]  Akira Miyoshi,et al.  Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation , 1994, IEEE Trans. Computers.

[6]  David W. Matula,et al.  A 17 /spl times/ 69 bit multiply and add unit with redundant binary feedback and single cycle latency , 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

[7]  Peter Kornerup Digit-Set Conversions: Generalizations and Application , 1994, IEEE Trans. Computers.

[8]  A. Avizeinis,et al.  Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .

[9]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[10]  O. L. Macsorley High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.

[11]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[12]  P. Chai,et al.  A 120 MFLOPS CMOS floating-point processor , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.