Very-Low-Voltage and Cross-Submicron-Technology Passive Tag＇s Logic Design

A low-voltage wide-tolerance-range passive UHF RFID tag's baseband logic design is presented in this paper. Based on deep submicron CMOS technologies, the design utilizes tailored techniques to satisfy subthreshold operation: to deal with the specific timing and wide-range- variation problems at very low power supply, and for the consideration of limited availability of RF power. Compen- sated addition is proposed for the PIE decoder, and power- aware scheme is applied to the entire logic part. Galoi Lin- ear feedback shift register (LFSR) and one-hot counter are also applied to fulfill critical timing requirements. Addi- tionally, these techniques help to improve clock efficiency and reduce the frequency variation impact in low-voltage data link portions. Therefore the robustness in subthresh- old operation is ensured. The logic design was fabricated in 180nm, 130nm and 90nm CMOS technologies respectively to verify the compatibility. In measurement the designs in- dicate competent subthreshold operation. The 90nm ver- sion can function at 0.33V.

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