29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces
暂无分享,去创建一个
[1] Takashi Masuda,et al. 10.4 A 12Gb/s 0.9mW/Gb/s wide-bandwidth injection-type CDR in 28nm CMOS with reference-free frequency capture , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).
[2] Koichi Yamaguchi,et al. A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[3] Deog-Kyoon Jeong,et al. A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit , 2011, 2011 IEEE International Solid-State Circuits Conference.
[4] Andrew Stewart,et al. 10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).
[5] Byungsub Kim,et al. 2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).