A z-domain model and analysis of phase-domain all-digital phase-locked loops

In this paper a comprehensive z-domain model of all-digital phase-locked loops (ADPLLs) is derived. The model accounts for phase and frequency signals and thus reflects both, frequency and phase behavior. The system model is investigated in detail. Each component is described in form of its transfer function to obtain an overall input/output behavior for the frequency and the phase domain. Furthermore, the physical characteristics of the noise sources within the structure are studied and their effects on the phase noise of the PLL are determined. The system level model is independent of the actual implementation, however, the relation to an existing frequency synthesizer for wireless communications is discussed. Simulation results confirm the accurateness of the presented model with respect to the time and frequency behavior of the system.

[1]  Poras T. Balsara,et al.  Event-driven Simulation and modeling of phase noise of an RF oscillator , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Roland E. Best.  Phase-Locked Loops , 1984 .

[3]  M. Nakagawa,et al.  A new PLL frequency synthesizer with high switching speed , 1992 .

[4]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[5]  R.B. Staszewski,et al.  TDC-based frequency synthesizer for wireless applications , 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.

[6]  Roland E. Best.  Phase-locked loops : design, simulation, and applications , 2003 .

[7]  S. Dondi,et al.  High-Level Design Flow for All-Digital PLLs , 2006, 2006 NORCHIP.

[8]  G. Baudoin,et al.  Time behavioral model for phase-domain ADPLL based frequency synthesizer , 2006, 2006 IEEE Radio and Wireless Symposium.

[9]  P. Gregorius,et al.  A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS , 2005, IEEE Journal of Solid-State Circuits.

[10]  Pavan Kumar Hanumolu,et al.  A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Poras T. Balsara,et al.  Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[12]  Poras T. Balsara,et al.  Phase-domain all-digital phase-locked loop , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[13]  O. Moreira-Tamayo,et al.  All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.

[14]  Floyd M. Gardner,et al.  Interpolation in digital modems. I. Fundamentals , 1993, IEEE Trans. Commun..