THOR - The hardware onion router

Security and privacy of data traversing internet have always been a major concern for all users. In this context, The Onion Routing (Tor) is the most successful protocol to anonymize global Internet traffic and is widely deployed as software on many personal computers or servers. In this paper, we explore the potential of modern reconfigurable devices to efficiently realize the Tor protocol on embedded devices. In particular, this targets the acceleration of the complex cryptographic operations involved in the handshake of routing nodes and the data stream encryption. Our hardware-based implementation on the Xilinx Zynq platform outperforms previous embedded solutions by more than a factor of 9 with respect to the cryptographic handshake - ultimately enabling quite inexpensive but highly efficient routers. Hence, we consider our work as a further milestone towards the development and the dissemination of low-cost and high performance onion relays that hopefully ultimately leads again to a more private Internet.

[1]  Hugo Krawczyk,et al.  HMAC-based Extract-and-Expand Key Derivation Function (HKDF) , 2010, RFC.

[2]  Ian Goldberg On the Security of the Tor Authentication Protocol , 2006, Privacy Enhancing Technologies.

[3]  Paul F. Syverson,et al.  Improving Efficiency and Simplicity of Tor Circuit Establishment and Hidden Services , 2007, Privacy Enhancing Technologies.

[4]  Luca Benini,et al.  Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ , 2013 .

[5]  Stephen T. Kent,et al.  Security Architecture for the Internet Protocol , 1998, RFC.

[6]  Roger Dingledine,et al.  Performance Improvements on Tor or, Why Tor is slow and what we're going to do about it , 2009 .

[7]  Hongyi Chen,et al.  A Gbps IPSec SSL Security Processor Design and Implementation in an FPGA Prototyping Platform , 2010, J. Signal Process. Syst..

[8]  Ian Goldberg,et al.  Anonymity and one-way authentication in key exchange protocols , 2012, Designs, Codes and Cryptography.

[9]  Jens-Peter Kaps,et al.  Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs , 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

[10]  Daniel J. Bernstein,et al.  Curve25519: New Diffie-Hellman Speed Records , 2006, Public Key Cryptography.

[11]  John W. Lockwood,et al.  IPSec implementation on Xilinx Virtex-II Pro FPGA and its application , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[12]  M. N. Marsono,et al.  Hardware Acceleration of OpenSSL Cryptographic Functions for High-Performance Internet Security , 2010, 2010 International Conference on Intelligent Systems, Modelling and Simulation.

[13]  Peter Schwabe,et al.  NEON Crypto , 2012, CHES.

[14]  Paul E. Hoffman,et al.  Cryptographic Suites for IPsec , 2005, RFC.

[15]  Paul F. Syverson,et al.  Hiding Routing Information , 1996, Information Hiding.

[16]  Tim Güneysu,et al.  Efficient Elliptic-Curve Cryptography Using Curve25519 on Reconfigurable Devices , 2014, ARC.

[17]  M. McLoone,et al.  A single-chip IPSEC cryptographic processor , 2002, IEEE Workshop on Signal Processing Systems.

[18]  Hugo Krawczyk,et al.  A Security Architecture for the Internet Protocol , 1999, IBM Syst. J..