A 360 MHz 3 V CMOS PLL with 1 V peak-to-peak power supply noise tolerance

In high-resolution graphics display devices, the jitter performance of phase-locked loops (PLL) limits the system performance. Power-supply noise coupling is a major cause of PLL jitter problems, especially with low-supply voltages and with multiple-clock synthesizers on the same device. This paper describes a 28- to 360 MHz 3.3 V PLL that uses a 0.5 /spl mu/m triple-metal digital CMOS process. The design uses a source follower VCO circuit combined with on-chip loop filter to achieve ac power supply noise tolerance up to 1 V peak-to-peak. This high-noise immunity design allows the PLL power supply to be directly connected to the digital VDD and GND on a mixed analog/digital chip. The PLL is implemented on a 600 k MOS transistor mixed-signal chip for high-speed data transfer clock and video clock generation. The power consumption for the PLL part is 3 mA when it is running at 250 MHz.