Improved Design and Analyse of Parallel Matrix Multiplication on Systolic Array Matrix

The prevailing of computer and Internet has brought demands for powerful and high performance data processing ways. However, in such complicated and heavy burden environment, fewer methods can provide perfect solution. To handle this problem, parallel computing is proposed as a solution to the contradiction. This paper deals with the problem and demonstrates an improved algorithm for the traditional Parallel Matrix Multiplication on Systolic Array, which is widely applied in the architecture of Central Processing Unit (CPU). It also analyzes and proves merits of the improvement. KeywordsWeb Systolic Array; Parallel Matrix Multiplication; Algorithm Efficiency