High Performance Packet Processor Architecture for Network Virtualization: Programmable Packet Processor Architecture as a Data Flow Machine

Network Processing differs from conventional computing such that it involves three steps; packet header parsing, lookup table match and action, de-parsing. Recently a language for programmable packet processors have been proposed. However, micro-architecture of existing packet processors still remains unchanged from the previous generation which has fundamental issue to support virtualization and separation of hardware and processes. This paper talks about one way of designing a packet processor based on data-flow micro-architecture to resolve two issues: Resource virtualization and Parallelism for packet processing. The research is still on-going, and presentation will cover the conceptual architecture of a packet processor which includes block level data-flow including connectivity and operators of the block.