论文信息 - Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector

Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector

This paper presents the techniques of shunt-peaking and active shunt-peaking as methods that can be used in the design of MCML gates. The use of these techniques opens the door to the design of high-speed gates that operate at frequencies where conventional MCML gates cease to function. To prove the concept, a half-rate linear phase detector was designed and submitted for fabrication using 0.18 /spl mu/m CMOS technology.

Yvon Savaria | Hung Tien Bui

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