Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

In this paper, we present a software framework that implements a formalized methodology for partitioning Digital Signal Processing applications between reconfigurable hardware blocks of different granularity. A hybrid generic reconfigurable architecture is considered, so that the methodology is applicable to a large variety of hybrid reconfigurable systems. The developed framework is composed of analysis, partitioning, and mapping tools. Although, the framework is parametrical in respect to the mapping procedures for the fine and coarse-grain reconfigurable units, we provide specific mapping algorithms for these types of hardware. In this work, the methodology is validated using five real-world digital signal processing applications; an orthogonal frequency division multiplexing transmitter, a cavity detector, a video compression technique, a JPEG encoder, and a wavelet-based image compressor. The experiments report that an average clock cycles decrease of 60.7%, relative to an all fine-grain mapping solution, is achieved using the developed framework for the considered applications.

[1]  Ahmadreza Rofougaran,et al.  A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard , 2003, IEEE J. Solid State Circuits.

[2]  Spyros Tragoudas,et al.  A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels , 2005, J. Circuits Syst. Comput..

[3]  Frank Vahid,et al.  Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic , 2002, IEEE Des. Test Comput..

[4]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[5]  Hideharu Amano,et al.  WASMII: a data driven computer on a virtual hardware , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[6]  Reiner W. Hartenstein,et al.  Parallelization in co-compilation for configurable accelerators-a host/accelerator partitioning compilation method , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

[7]  Majid Sarrafzadeh,et al.  Instruction generation for hybrid reconfigurable systems , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[8]  Frank Vahid,et al.  Energy savings and speedups from partitioning critical software loops to hardware in embedded systems , 2004, TECS.

[9]  John Wawrzynek,et al.  The Garp Architecture and C Compiler , 2000, Computer.

[10]  Gerard J. M. Smit,et al.  Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture , 2004, The Journal of Supercomputing.

[11]  Masato Motomura,et al.  An Embedded DRAM-FPGA Chip With Instantaneous Logic Reconfiguration , 1997, Symposium 1997 on VLSI Circuits.

[12]  Camel Tanougast,et al.  Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system , 2003, Microprocess. Microsystems.

[13]  João M. P. Cardoso.  On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures , 2003, IEEE Trans. Computers.

[14]  Michael D. Smith.  The Machine-SUIF SUIFvm Library , 2002 .

[15]  Doug Brown,et al.  Lex and Yacc , 1990 .

[16]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[17]  Majid Sarrafzadeh,et al.  Instruction generation and regularity extraction for reconfigurable processors , 2002, CASES '02.

[18]  M. Bister,et al.  Automated segmentation of cardiac MR images , 1989, [1989] Proceedings. Computers in Cardiology.

[19]  Prithviraj Banerjee,et al.  A C compiler for a processor with a reconfigurable functional unit , 2000, FPGA '00.

[20]  Frank Vahid,et al.  SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[21]  Peter M. Athanas,et al.  A run-time reconfigurable engine for image interpolation , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[22]  George Varghese,et al.  Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System , 2001, J. VLSI Signal Process..

[23]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[24]  Ranga Vemuri,et al.  An Automated Temporal Partitioning Tool for a class of DSP applications , 1998, PACT 1998.

[25]  Jörg Henkel.  A low power hardware/software partitioning approach for core-based embedded systems , 1999, DAC '99.

[26]  Frank Vahid,et al.  Profiling tools for hardware/software partitioning of embedded applications , 2003, LCTES.