GASIM: a fast Galois field based simulator for functional model

This paper presents a fast logic simulator based on Galois field. This is designed to act as an underlying tool for all finite field applications considering the fact that simulation plays an important role in all these applications. Three approaches for finite field representation and its evaluation are discussed. In addition an approach for normalizing the finite field based decision diagrams is also presented. The experimental results show the trade-off that can be made by using different design representations between spatial complexity and speed. Also the results show that it can be used in conventional simulation environment to achieve speedup.

[1]  Masahiro Fujita,et al.  On variable ordering of binary decision diagrams for the application of multi-level logic synthesis , 1991, Proceedings of the European Conference on Design Automation..

[2]  A.L. Sangiovanni-Vincentelli,et al.  Fast discrete function evaluation using decision diagrams , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[3]  William Stallings,et al.  Cryptography and network security , 1998 .

[4]  Randal E. Bryant.  Binary decision diagrams and beyond: enabling technologies for formal verification , 1995, ICCAD.

[5]  Dhiraj K. Pradhan,et al.  MODD: a new decision diagram and representation for multiple output binary functions , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  Chien-Ming Wu,et al.  High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m) , 2004, IEEE Trans. Computers.

[7]  R. Bryant,et al.  Verification of Arithmetic Functions with Binary Moment Diagrams , 1994 .

[8]  Tiziano Villa,et al.  Multi-valued decision diagrams: theory and applications , 1998 .

[9]  Rolf Drechsler,et al.  Functional simulation using binary decision diagrams , 1997, ICCAD 1997.

[10]  Tsutomu Sasao,et al.  Comparison of Decision Diagrams for Multiple-Output Logic Functions , 2002, IWLS.

[11]  R. Bryant.  Binary decision diagrams and beyond: enabling technologies for formal verification , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[12]  Richard E. Blahut,et al.  Fast Algorithms for Digital Signal Processing , 1985 .

[13]  D. Michael Miller.  Multiple-valued logic design tools , 1993, [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic.

[14]  Robert K. Brayton,et al.  Software synthesis from synchronous specifications using logic simulation techniques , 2002, DAC '02.

[15]  Randal E. Bryant,et al.  Verification of Arithmetic Circuits with Binary Moment Diagrams , 1995, 32nd Design Automation Conference.

[16]  Dhiraj K. Pradhan,et al.  Mathematical framework for representing discrete functions as word-level polynomials , 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

[17]  Shin-ichi Minato,et al.  Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems , 1993, 30th ACM/IEEE Design Automation Conference.

[18]  Dhiraj K. Pradhan.  A Theory of Galois Switching Functions , 1978, IEEE Transactions on Computers.

[19]  S. Wicker.  Error Control Systems for Digital Communication and Storage , 1994 .

[20]  Alexander Saldanha,et al.  Fast discrete function evaluation using decision diagrams , 1995, ICCAD.

[21]  Eduard Cerny,et al.  Simulation of MOS Circuits by Decision Diagrams , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.