Area and frequency optimized 1024 point Radix-2 FFT processor on FPGA

This paper presents a Fast Fourier Transform (FFT) processor optimized for both ‘area’ and ‘frequency’. The processor architecture is deeply pipelined Radix-2 butterfly unit, 1024 point, 64bit Fixed Point input with 32bit real and 32bit imaginary, Decimation In Time (DIT) FFT processor on Field Programmable Gate Array (FPGA). The proposed architecture is based on Dual RAM Ping-Pong Burst I/O with efficient addressing techniques which clocks at 385.804MHz on Xilinx Virtex-6 xc6vlx550t-2ff1759 taking 16.376µs to calculate one set of 1024 point FFT.

[1]  Jack E. Volder The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[2]  T. Sansaloni,et al.  Efficient FPGA implementation of Cordic algorithm for circular and linear coordinates , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[3]  J. Tukey,et al.  An algorithm for the machine calculation of complex Fourier series , 1965 .

[4]  Weng Fook Lee Verilog Coding for Logic Synthesis , 2003 .

[5]  Uwe Meyer-Baese,et al.  Digital Signal Processing with Field Programmable Gate Arrays , 2001 .

[6]  John D. Davis,et al.  BLAS Comparison on FPGA, CPU and GPU , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[7]  Alan V. Oppenheim,et al.  Discrete-Time Signal Pro-cessing , 1989 .