AUTOMATIC FORMAL VERIFICATION OF DIGITAL SYSTEMS USING PROLOG

An approach for automatic formal verification of digital hardware designs named VERDIS is presented. Validation of design correctness is made by formal proof as an alternative to the traditional approach which utilizes simulation. A hardware design methodology based on this framework entails:a) writing a specification of required design,b) designing a circuit intended to implement it,c) proving mathematically that the design meets its specification.