Interprocedural parallelization using memory classification analysis

This thesis outlines a way of addressing the goal of pre ise interpro edural analysis, based on a ombination of te hniques: for representing memory a esses within interpro edural se tions of ode, for summarizing dependen e information in program ontexts, and for testing that dependen e. The thesis presents a new te hnique for summarizing the memory a ess a tivity in an arbitrary se tion of ode, alled Memory Classi ation Analysis (MCA), using a pre ise form for representing memory a ess patterns, alled the A ess Region Des riptor (ARD). A new, simple dependen e test, the A ess Region Test (ART), is also des ribed whi h uses the summary sets of ARDs produ ed by MCA. This test is apable of parallelizing loops ontaining non-aÆne subs ript expressions, su h as those found in FFT odes. A uni ed parallelization framework is des ribed, whi h ombines privatization, redu tion and indu tion analysis. Array referen es using subs ripting arrays, su h as are found in sparse odes are pre isely representable using ARDs, and an sometimes be parallelized using the parallelization framework. Parallelization onditions are generated at riti al points in the analysis when dependen e annot be disproved. These an be used to drive on-demand deeper program analysis. Whatever onditions remain unproven an then be generated as ode to be used for runtime dependen e testing. Its pre ise memory a ess representation makes the ARD useful within algorithms for generating data movement messages. iii To my loving wife Donna and my wonderful teenagers, Chris and Dan, for all the sa ri es you have had to make, just be ause \I wanna be a do tor". Thanks for the love, for putting up with me, and for dragging me away from my work into the real world at regular intervals. And To my parents, Aug and Rose Hoe inger, whose love and support never wavered, and who taught me that anything is possible through hard work. I herish all of you.