CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation

This paper describes a reference-clock-free, high-time-resolution on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier (TDA) with duty-cycle compensation. A self-referenced clock with multiples of the clock period removes the necessity for a reference clock. In addition, a cascaded TDA with duty-cycle compensation improves the time resolution while maintaining the operational speed. Test chips were designed and fabricated using 65 nm and 40 nm CMOS technologies. The areas occupied by the circuits are 1350 μm2 (with TDA, 65 nm), 490 μm2 (without TDA, 65 nm), 470 μm2 (with TDA, 40 nm), and 112 μm2 (without TDA, 40 nm). Time resolutions of 31 fs (with TDA) and 2.8 ps (without TDA) were achieved. The proposed new architecture provides all-digital timing jitter measurement with fine-time-resolution measurement capability, without requiring a reference clock.

[1]  Kenneth L. Shepard,et al.  On-Chip Circuit for Measuring Period Jitter and Skew of Clock Distribution Networks , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[2]  Hong-June Park,et al.  A 0.63ps resolution, 11b pipeline TDC in 0.13µm CMOS , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[3]  Aubin Roy,et al.  BIST for phase-locked loops in digital applications , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[4]  K. Jenkins,et al.  An on-chip jitter measurement circuit with sub-picosecond resolution , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[5]  John A. McNeill.  Jitter in ring oscillators , 1997 .

[6]  Keith A. Jenkins,et al.  A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset , 2009, 2009 27th IEEE VLSI Test Symposium.

[7]  Kunihiro Asada,et al.  A New Procedure for Measuring High-Accuracy Probability Density Functions , 2012, 2012 IEEE 21st Asian Test Symposium.

[8]  K. Ichiyama,et al.  A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[9]  Kamilo Feher,et al.  Telecommunications Measurements, Analysis, and Instrumentation , 1987 .

[10]  Kuo-Hsing Cheng,et al.  A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique , 2011, IEEE Journal of Solid-State Circuits.

[11]  Mani Soma,et al.  Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method , 2003 .

[12]  T. Cho,et al.  A low spur fractional-N digital PLL for 802.11 a/b/g/n/ac with 0.19 psrms jitter , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[13]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.

[14]  Takahiro J. Yamaguchi,et al.  Skew measurements in clock distribution circuits using an analytic signal method , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Shinji Nishimura,et al.  A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link , 2011, IEEE Journal of Solid-State Circuits.

[16]  T.Y. Nguyen,et al.  On-chip jitter and oscilloscope circuits using an asynchronous sample clock , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

[17]  Takahiro J. Yamaguchi,et al.  A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[18]  M. Curtin,et al.  Phase-Locked Loops for High-Frequency Receivers and Transmitters – Part 2 by , 1999 .