On the design of bit-interleaved turbo-coded modulation with low error floors

In this paper, we introduce an algorithm to optimize the performance in the error-floor region of bit-interleaved turbo-coded modulation (BITCM) on the additive white Gaussian noise channel. The key ingredient is an exact turbo code weight distribution algorithm producing a list of all codewords in the underlying turbo code of weight less than a given threshold. In BITCM, the information sequence is turbo-encoded, bit-interleaved, and mapped to signal points in a signal constellation. Using the union-bounding technique, we show that a well-designed bit interleaver is crucial to have a low error floor. Furthermore, the error-rate performance in the waterfall region depends on the bit interleaver, since the level of protection from channel noise on the bit level depends on the bit position and the neighboring bit values within the same symbol in the transmitted sequence. We observe a tradeoff between error-rate performance in the waterfall and error-floor regions, as illustrated by an extensive case study of a high-rate BITCM scheme. This tradeoff is typical in iterative decoding of turbo-like codes. The reported case study shows that it is possible to design bit interleavers with our proposed algorithm with equal or better performance in the waterfall region and superior performance in the error-floor region, compared with randomly generated bit interleavers. In particular, we were able to design BITCM schemes with maximum-likelihood decoding frame-error rates of 10-12 and 10 -17 at 2.6 and 3.8 dB away from unconstrained channel capacity, at spectral efficiencies of 3.10 and 6.20 b/s/Hz using square 16 and 256-quadrature amplitude modulation signal constellations, respectively