On fault tolerance of hardware samplers

In this research, we evaluate the robustness of hardware samplers to hardware faults. This study was motivated by our observation that several applications use sampling as a primitive and that sampling itself is an approximate method for computation. As such, it might be possible to lower energy consumption of hardware implementations of applications by implementing the samplers using more energy efficient, but fault prone, devices. We implemented a sampler in hardware and characterized its output quality in the presence of stuck-at faults and transient faults using an FPGA based gate level fault injection methodology. To understand the application level implications of such errors made by the sampler, we studied its impact on two applications: particle filtering and clustering using a Dirichlet Process Mixture Model (DPMM). Our results indicate that hardware samplers are indeed robust to hardware faults and that their robustness improves in the context of application level metrics. Specifically, we observed that (a) the two applications can tolerate multiple stuck-at faults in the sampler ( > 5 faults at the same time), (b) the applications can tolerate gate level transient fault rates as high as 2.4 × 10−4, and (c) only faults in a small number of gates (< 5.2%) affect the output quality of the applications. The results show that there may be significant promise to leveraging this robustness to implement sampling based applications with much higher energy efficiency than what was previously thought possible.