Randomly Optimized Grid Graph for Low-Latency Interconnection Networks

In this work we present randomly optimized grid graphs that maximize the performance measure, such as diameter and average shortest path length (ASPL), with subject to limited edge length on a grid surface. We also provide theoretical lower bounds of the diameter and the ASPL, which prove optimality of our randomly optimized grid graphs. We further present a diagonal grid layout that significantly reduces the diameter compared to the conventional one under the edge-length limitation. We finally show their applications to three case studies of off-and on-chip interconnection networks. Our design efficiently improves their performance measures, such as end-to-end communication latency, network power consumption, cost, and execution time of parallel benchmarks.

[1]  Toshiyuki Shimizu,et al.  Tofu: A 6D Mesh/Torus Interconnect for Exascale Computers , 2009, Computer.

[2]  David H. Bailey,et al.  The Nas Parallel Benchmarks , 1991, Int. J. High Perform. Comput. Appl..

[3]  Henri Casanova,et al.  Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects , 2015, IEEE Transactions on Parallel and Distributed Systems.

[4]  N.D. Arora,et al.  Interconnect characterization of X architecture diagonal lines for VLSI design , 2005, IEEE Transactions on Semiconductor Manufacturing.

[5]  William J. Dally,et al.  Flattened Butterfly Topology for On-Chip Networks , 2007, IEEE Comput. Archit. Lett..

[6]  Natalie D. Enright Jerger,et al.  Dodec: Random-Link, Low-Radix On-Chip Networks , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[7]  Torsten Hoefler,et al.  Slim Fly: A Cost Effective Low-Diameter Network Topology , 2014, SC14: International Conference for High Performance Computing, Networking, Storage and Analysis.

[8]  Henri Casanova,et al.  A case for random shortcut topologies for HPC interconnects , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[9]  Antonio Robles,et al.  A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms , 2012, IEEE Transactions on Parallel and Distributed Systems.

[10]  William J. Dally,et al.  Design tradeoffs for tiled CMP on-chip networks , 2006, ICS '06.

[11]  George Michelogiannakis,et al.  Elastic-buffer flow control for on-chip networks , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[12]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[13]  V. G. Cerf,et al.  A lower bound on the average shortest path length in regular graphs , 1974, Networks.

[14]  聡 藤田,et al.  開催報告(Graph Golf) , 2016 .

[15]  Anantha Chandrakasan,et al.  Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks , 2013, Computer.

[16]  Henri Casanova,et al.  Versatile, scalable, and accurate simulation of distributed applications and platforms , 2014, J. Parallel Distributed Comput..

[17]  William J. Dally,et al.  Technology-Driven, Highly-Scalable Dragonfly Topology , 2008, 2008 International Symposium on Computer Architecture.

[18]  J. P. Grossman,et al.  Unifying on-chip and inter-node switching within the Anton 2 network , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[19]  David H. Bailey,et al.  The Nas Parallel Benchmarks , 1991, Int. J. High Perform. Comput. Appl..