A low-power CMOS power amplifier for IEEE 802.11a applications

A low-power fully-integrated power amplifier (PA) for IEEE 802.11a applications is designed with 0.18µm radio frequency CMOS process. A folded cascode structure is adopted to reduce the supply voltage. The driver stage acts as a preamplifier which is composed of an inverse amplifier with a gate-driving circuit. The peak power-added efficiency (PAE) is 24.5% at 3V supply voltage. The output 1dB compression point OP1dB is 20.5dBm. The saturated output power achieves 21.8dBm at 5.2GHz. The biasing current of 114mA and 167mA are consumed at quiescent point and P1dB, respectively. The power gain within the linear operating range is 20.3dB. The maximum output power is 21dBm. The maximum PAE is 24.5%.

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