A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage AS interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q 2 Random Walk switching scheme. The ΔΣ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage AS noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-μm CMOS technology with active area of 1.11 mm 2 including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm 2 . The total power consumption of the DDFS is 200 mW with a 3.3-V power supply.

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