Online Evolvable Pattern Recognition Hardware

We propose an evolvable hardware (EHW) architecture for pattern recognition. Compared to an earlier offline EHW pattern recognition approach, the proposed architecture is advantageous in its suitability for online adaptation while maintaining a very high recognition speed. With its support for virtual run-time reconfiguration, the architecture is suitable for implementation in an on-chip evolution system. Function level modules and data buses are employed in the architecture in order to reduce the search space. Furthermore, incremental evolution is applied, which shortens evolution time and allows for the evolution of a larger system. The use of incremental evolution also has the advantage of reducing the size of the evolution hardware in an on-chip evolution system. Variations in architecture parameters are explored, and it is found that the size of the system can be reduced at the cost of longer evolution time or lower recognition accuracy. The architecture is applied to a face image recognition task, for which a recognition accuracy of 96.25% is demonstrated. This result is better than the previously proposed offline EHW architectures.

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